When should one send EOC from a sequencer?

Say you have 4 steps, and it’s looping. Especially if you want to reset a second sequencer when the first one loops around?

Does the EOC go high immediately when the sequencer gets a clock to send it from step 4 back to step 1? But if you do that the EOC will come after the clock, and the second sequencer will seem to start from step 2. Not good.

If you are using the “nord style” reset, then the EOC should be send any time during step 4, then both sequencers can start together on step 1 (assuming the share a common clock).

Or does EOC just not work from sequencer to sequencer? Enquiring minds want to now how this is supposed to work.

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This is my favorite way to hookup sequencers of this style. by using the end of sequence signal to reset the following sequencer in one-shot mode.

how the expanders work is outstanding also - just an odd flash on the expander sometimes - not sure what causes the glitch.

EOC is a usually found on a function generator when the function completes a cycle, correct?. I would think that on a sequencer EOC should go high after the last step’s trigger is fired, low after first trigger.

@CountModula or @marc_boule - you guys know all about this stuff. Ideas?

EOC on a sequencer should fire at the end of the last step. It effectively corresponds to the start of step 1 but doesn’t fire the first time through or if the sequencer is reset before the last step has completed. Length of EOC output would depend on the sequencer mode and the developers wishes. For example, EOC is not used on my normal sequencers unless they are in 1-shot mode. On my Euclidean Sequencer it is a trigger pulse.


Agreed, I see it like this also.

Sure, but when do you send OEC relative to the clock? Is the idea that you send OEC one sample after the clock, so for downstream sequencers the clock will occur, sending them back to the first step (if they are already in sync), then on the next sample they will get the EOC and reset again to the first step, thus playing correctly?

I guess this is how “classic” reset works? the clock and the reset are received at “more or less” the same time, and as long as the receiver ignores clocks within 1 MS of reset the receiver will correctly start on the first step?

Yep, EOC goes out on the next sample, same as the sequencer advancing to the next step.

well, I can’t say this protocol gives me “warm fuzzies”, but it should work if everyone obeys the “1 ms” guideline.

in my sequencer I send the End signal after the last step. but I check Start before I check the clock status so I know my next sequencer should be running before I see the clock.

Could you explain that algorithm more?