So today is a day of questions… bear with me.
Anyways so I am working on this patch. Essentially what is happening is that the Clocked Module is feeding different BPM’s into various sequential switches. It’s a Sequential Switches inside of Sequential switches type patch… anyways… the Clocked module is responsible for both the ‘reset’ and also the 'up" (on the ML Module 8 > 1) . i am using a Manual Trigger to both RUN / RESET the Clocked module. The idea being that all the sequential switches start on the first Switch (pattern 1). But what inevidably happens is that the Sequential Switches all start on the 2nd switch and not the first. The reason being is that the clocked module is also responsible for the Seqencing of the switches “up” in this case.
Any simple work around to this problem? I simply want all the sequential switches to begin ont he first switch, iike hitting the 'run" button on a sequencer. But the ‘reset’ in combo with the ‘up’ is getting in my way… =/ help
That’s weird… I just tried this and it start from the first step, not from the second one. Anyway, I think that the easiest will be to set all the switches to their last step, so when you start the clock it will jump one step forwards, to the first step. But as I said, it behaves differently on my end. Would you mind sharing this part of the patch?
starting on 2nd weird.vcv (18.2 KB)
Thx Omri, here’s the file.
It might be how the patch is set up? A few Clocked modules too manny? I just tried it in a new patch with less thigns going on and it reset just normally.
to get around this sort of thing I sometimes wire up both the run and the reset signal to the reset of the module.
starting on 2nd weird 2.vcv (19.0 KB)
How nice JimT. I’m not sure why that works but it does… and I’m noto sure what is causing this issue, since i don’t have it when using less modules…
That’s so weird… But Jim’s version seems to work fine, combining the signals. I wonder what’s the issue here. Maybe it’s the samples delay…
I get it with very basic usage: starting on 2nd weird 3.vcv (3.6 KB)
It makes sense in a way, although it’s not really useful: reset moves to the first input, a signal to “up” moves to the next input. So using a clock, reset moves to input 1, first clock to input 2.
What the previous patch does is merge the reset and run signals, so when either “run” or “reset” is pressed, the reset gets triggered in the sequential switches, effectively pinning it to input 1 for the first clock cycle.