Interesting thread, I came up against a case today in my research on how clocks and sequencers behave in modular, and this post seems to have a common point regarding re-triggers. (I get to re-triggers a bit further down in my comment)
I’m actually studying the impacts of a change in Clocked regarding what levels its clock outputs should be in, after resetting a stopped clock. I inevitably come to the conclusion that they must be high so that when we turn on run again (on the clock) at a later time, there will be no rising edge on those clocks that would trigger a sequential switch to immediately move to the next step (and missing the first one). This also makes Clocked behave more like an LFO, which starts off in a high state after reset. Here is the case that is well behaved if and only if Clocked resets its outputs high:
But with this new change, when connecting Clocked to a sequencer, if we reset a stopped Clocked and then start it up again, or even in the current version if we reset a running Clocked while its output is high, in such cases the gate of the 1st step (provided it is turned on) will not produce a trigger because it has stayed continually on. I am considering (and testing) an implicit re-trigger so that anytime a reset is received by the sequencer, it momentarily brings the GATE outputs low for 1ms and then the rest of the gate continues as normal. Although this might appear like a hack, it seems to be working very well so far, and it’s the only way I have found yet to get some good reset behavior out of my sequencers’ gates.
Just putting this out there in case anyone wants to discuss, or perhaps even to test the new version if interested.