The VCA is being used effectively as an AND gate, and I was able to get the same behavior using this setup:
It could be possible to add an option to make the clock input serve as an enable on the write, thus avoiding the need for the 3HP bool module (or VCV VCA), but I’ll think about this more before making any changes to see what would be optimal qantization-wise. As things are in the current setup, hitting a key real quicly while the clock is low (and relasing the key before the next clock edge) will result in the given note being undetected by the PS16 (and thus not written).