I have some gates in a sequence, for example1,2,3,4 and 5. I’d like to kill gate 4, so the sequence becomes 1\,2,3 and 5. I’ve tried using a counter (AS STEPS) generating a gate on number 4, then combining with logic modules the complete sequence and the gate from the counter, but I can’t get it
You are definitely on the right track. There are many ways to do this, but they’re generally similar to what you’re doing.
Not familiar with AS Steps ( I use docB ACC or Artificialcolors Pul5es or CVFunk Count) but make sure it’s in loop mode, so it triggers on every 5th step.
And then you want to mute the gate output on step 4, so logic modules as you are using, or MOOTS.
One easy thing to miss is that the mute logic may arrive too late, after the gate signal. Because you are adding cables and 1 (audio frame rate, eg 48khz) clock tick for every cable and module in your mute path. To account for that you need to delay the gate signal just a few ticks. Grande VarSampleDelays is made exactly for this with a default delay of 5 ticks which is exactly what you need 90% of the time.
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Yeah, now it works. The trick in my case is first to normalize gate lenghts with Alikins module, then use VarSampleDelays as you suggested.