Can the release of an adsr influence a clock (bug) ?

VCV Rack
21

You are right and I am wrong. Sorry to cause confusion.

The VCV Voltage Standard for Trigger and Gate (high) in VCV Rack is pretty clear: 10 V (where a trigger lasts for 1 ms).

Triggers and Gates

In Eurorack, many modules are triggered by reaching a particular rising slope threshold. However, because of the Gibbs phenomenon, a digital emulation will falsely retrigger many times if the trigger source is bandlimited (e.g. by using a virtual VCO square wave as a trigger input or a hardware trigger through an audio interface.)

Therefore, trigger inputs in Rack should be triggered by a Schmitt trigger with a low threshold of about 0.1 V and a high threshold of around 1 to 2 V. Rack plugins can implement this using dsp::SchmittTrigger with schmittTrigger.process(rescale(x, 0.1f, 2.f, 0.f, 1.f))

Trigger sources should produce 10 V with a duration of 1 ms. An easy way to hold a trigger for this duration is to use dsp::PulseGenerator with pulseGenerator.trigger(1e-3f).

Gates should produce 10 V when active.

Maybe it’s just the way various modules actually implement their trigger or gate (input) signal levels (thresholds). As far as I know, various modules trigger/gate at different levels. This is especially relevant when trigger/gate signals are generated from some ‘random’ source (like from noise and S&H). In that case you might put a VCA in between to have control over the chance that the trigger/gate level (for a specific module) is reached.

1 Like