SignalDelayModulation.vcv (12.0 KB)
Maybe this ‘example’ is more complicated than need be, but …
Then I’m using a VCV 4:1 Router to randomly select delay time CVs for the Signal Delay.
I like the results musically, but I’m having trouble visualizing how delay time modulation affects the trigger outputs.
You have a stream of triggers going through the Signal Delay. When you change the delay time, the delay buffer size changes (I assume) - but what happens to the currently buffered triggers?
It’s kind of a Zen question: where does the time go when you change the delay time?
I think if you go from a short delay to a long delay, it just means the currently buffered triggers happen later. If you go from a long delay to a short day, is it throwing away buffered-but-not-yet-emitted triggers?
[EDIT] I actually put a scope on the triggers and it is instructive. It really looks like AS Signal delay just changes the buffer size and keeps going. There artifacts of this, like if the delay time changes while a gate is high it will go to zero, meaning some delayed gates are shortened.
I just wonder what the delay does with its internal ‘read head.’ If you go from a short to a long delay, the read head can keep going from its current position. But if you go from long to short, the read head points past the end of the buffer.
Is it reset to the start of the buffer (the only safe option IMO) or is it set to the same proportional position in the shorter buffer? And beyond what it actually does, what SHOULD it do?
This may seem like a ridiculous waste of attention to something that I can just go ahead and use without knowing exactly what’s happening. But my monkey brain wants to understand, and is being defeated.